Experience

Technologies we have modeled

 

Leadframe

Wirebond

Flip chip

Multi-die wire bond

Multi-die flip chip

Fan-in (WLCSP)

Fan-out (SWIFT-style, SLIM-style, eWLB-style, InFO-style, and others)

Chip-first fan-out

Chip-last fan-out

Multi-die fan out

Fan-out with die stacking

Through mold vias

Die to wafer stacking (D2W)

Wafer to wafer stacking (W2W)

2.5D

Chip on interposer on substrate

Via-first

Via-middle

Via-last

Embedded technologies

Panel level packaging

Screen printed electronics

Flexible electronics

Examples of activities in the SavanSys library

 

Subtractive, Additive, mSAP, SAP substrate processes

Coreless substrates

Copper pillar bumping

Solder bumping
Hybrid bonding

All common surface finishes

Wedge bonding, Stitch bonding, Cascade bonding

Laser vias, Mechanical vias

CVD, PVD

LDI, Stepper and aligner imaging

High density interconnect (HDI)

Cavity creation

Embedded passives, fabricated passives

Though silicon vias (TSVs)

Transfer molding, compression molding

Wafer-level molding

Visit the Consulting Projects section for a list of projects we have done.

© 2020 by SavanSys Solutions LLC.