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On this page, papers and/or slides that have been published at various conferences are listed. There are also links to articles that SavanSys has authored. Technical papers  must be accessed on a private page; please complete the user form to load the links for the Technical Papers.

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Technical Papers/Presentations

IC Packaging

Cost and Yield Considerations of 2.5D and Fan-out on Substrate Technologies (2020)

Cost Comparison of Panel Level and Wafer Level Fan-out Packaging (2019)

Comparison of Package-on-Package Technologies Utilizing Flip Chip and Fan-Out Wafer Level Packaging (2018)

Cost and Yield Analysis of RDL Creation in Fan-out Wafer Level Packaging (2018)

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging (2017)

Yield Comparison of Die-first Face-Down and Die-last Fan-out Wafer Level Packaging (2017)

A Cost Analysis of RDL-first and Mold-first Fan-out Wafer Level Packaging (2016)

Cost Analysis of a Wet Etch TSV Reveal Process (2016)

Cost Comparison of Fan-out Wafer-Level Packaging to Fan-out Panel-Based Packaging (2016)

Cost and Yield Analysis of Wafer-to-wafer Bonding (2015)

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste (2015)

Cost Comparison of Temporary Bond and Debond Methods For Thin Wafer Handling (2014)

Cost Comparison of 2.5D/3D Packaging to other Packaging Technologies (2013)

Embedded Passives

A Comparison of Small Discretes and Polymer Thick Film Embedded Resistors for Mobile Phone Applications (2013)

Activity Based Cost Modeling for Embedded Passives (2012)

Fabrication and Assembly Yield for Embedded Passives: Risks and Opportunities (2012)

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